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? semiconductor components industries, llc, 2010 march, 2010 ? rev. 0 1 publication order number: ADP3209D/d ADP3209D 5-bit, programmable, single-phase, synchronous buck controller the ADP3209D is a highly efficient, single ? phase, synchronous buck switching regulator controller. with its integrated drivers, the ADP3209D is optimized for converting the notebook battery voltage to render the supply voltage required by high performance intel chipsets. an internal 5 ? bit dac is used to read a vid code directly from the chipset and to set the gmch core voltage to a value within the range of 0.4 v to 1.25 v. the ADP3209D uses a multi ? mode architecture. it provides programmable switching frequency that can be optimized for efficiency depending on the output current requirement. in addition, the ADP3209D includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. the ADP3209D also provides accurate and reliable current overload protection and a delayed power ? good output. the ic supports on ? the ? fly (otf) output voltage changes requested by the chipset. the ADP3209D is specified over the extended commercial temperature range of 0 c to 100 c and is available in a 32 ? lead lfcsp. features ? single ? chip solution ? fully compatible with the intel ? gmch chipset voltage regulator specifications ? integrated mosfet drivers ? input voltage range of 3.3 v to 22 v ? 8 mv worst ? case differentially sensed core voltage error overtemperature ? automatic power ? saving modes maximize efficiency during light load operation ? soft transient control reduces inrush current and audio noise ? independent current limit and load line setting inputs for additional design flexibility ? built ? in power ? good masking supports voltage identification (vid) otf transients ? 5 ? bit, digitally programmable dac with 0.4 v to 1.25 v output ? short ? circuit protection with latchoff delay ? output current monitor ? 32 ? lead lfcsp ? this is a pb ? free device applications ? notebook power supplies for next ? generation intel chipsets marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 26 of this data sheet. ordering information lfcsp32 case 932ae ADP3209D awlyywwg a = assembly location wl = wafer lot yyww = date code g = pb ? free package pin assignment vid4 1 ADP3209D (top view) gnd pgnd drvl pvcc sw drvh bst vcc lline cscomp csref csfb ramp ilmin ilimp rt 9 17 25 32 24 16 8 fbrtn fb comp cref nc imon iref rpm en pwrgd vid3 vid2 vid1 vid0 varfreq
ADP3209D http://onsemi.com 2 figure 1. functional block diagram vid dac vid4 vid3 vid2 vid1 vid0 fbrtn pwrgd startup delay pwrgd pwrgd open drain + ? + ? + ? + ? csref dac + 200mv dac ? 300mv soft transient delay delay disable dac ? + ? + csref csfb cscomp ilim + ? + ? ovp csref 1.7 v + ? + ? _ + lline ref ref + + vea fb comp uvlo shutdown and bias uvlo vcc en gnd oscillator rpm rt ramp imon iref current monitor current bst drvh current limit circuit ocp shutdown delay sw pgnd drvl pvcc driver logic precision reference precision soft ? start varfreq absolute maximum ratings parameter rating unit vcc ? 0.3 to +6.0 v fbrtn, pgnd ? 0.3 to +0.3 v bst dc t < 200 ns ? 0.3 to +28 ? 0.3 to +33 v bst to sw ? 0.3 to +6.0 v sw dc t < 200 ns ? 5 to +22 ? 10 to +28 v drvh to sw dc ? 0.3 to +6.0 v drvl to pgnd dc t < 200 ns ? 0.3 to +6.0 ? 0.3 to +6.0 ? 5.0 to +6.0 v ramp (in shutdown) ? 0.3 to +22 v all other inputs and outputs ? 0.3 to +6.0 v storage temperature ? 65 to +150 c operating ambient temperature range 0 to 100 c operating junction temperature 125 c thermal impedance ( ja ) 2 ? layer board 32.6 c/w lead temperature soldering (10 sec) infrared (15 sec) 300 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling.
ADP3209D http://onsemi.com 3 pin function descriptions pin no mnemonic description 1 fbrtn feedback return input/output. this pin remotely senses the gmch voltage. it is also used as the ground return for the vid dac and the voltage error amplifier blocks. 2 fb voltage error amplifier feedback input. the inverting input of the voltage error amplifier. 3 comp voltage error amplifier output and frequency compensation point. 4 cref this pins sets the internal bias currents. connect an 80k resistor from either this pin or iref pin to ground. if an 80 k resistor is connected from this pin to ground, iref pin must remain floating. 5 nc not connected. 6 imon current monitor output. open ? drain output. this pin sources a current proportional to the output load current. a resistor from imon to fbrtn sets the current monitor gain. 7 iref this pins sets the internal bias currents. connect an 80 k resistor from either this pin or cref pin to ground. if an 80 k resistor is connected from this pin to ground, cref pin must remain floating. 8 rpm rpm mode timing control input. an external resistor between this pin to ground sets the rpm mode turn ? on threshold voltage. 9 lline load line programming input. the center point of a resistor divider connected between csref and cscomp can be tied to this pin to set the load line slope. 10 cscomp current sense amplifier output and frequency compensation point. 11 csref current sense reference input. this pin must be connected to the opposite side of the output inductor. 12 csfb non ? inverting input of the current sense amplifier. the combination of a resistor from the switch node to this pin and the feedback network from this pin to the cscomp pin sets the gain of the current sense amplifier. 13 ramp pwm ramp slope setting input. an external resistor from the converter input voltage node to this pin sets the slope of the internal pwm stabilizing ramp. 14 ilimn current limit set point. an external resistor between ilimn and ilimp sets the current limit set point. 15 ilimp current limit set point. an external resistor between ilimn and ilimp sets the current limit set point. 16 rt pwm oscillator frequency setting input. an external resistor from this pin to gnd sets the pwm oscillator frequency. 17 gnd analog and digital signal ground. 18 pgnd low ? side driver power ground. this pin should be connected close to the source of the lower mosfet(s). 19 drvl low ? side gate drive output. 20 pvcc power supply input/output of low ? side gate driver. 21 sw current return for high ? side gate drive. 22 drvh high ? side gate drive output. 23 bst high ? side bootstrap supply. a capacitor from this pin to sw holds the bootstrapped voltage while the high ? side mosfet is on. 24 vcc power supply input/output of the controller. 25 to 29 vid4 to vid0 voltage identification dac inputs. a 5 ? bit word (the vid code) programs the dac output voltage, the reference voltage of the voltage error amplifier without a load (see the vid code table, table 1). in normal operation mode, the vid dac output programs the output voltage to a value within the 0 v to 1.25 v range. the input is actively pulled down. 30 en enable input. driving this pin low shuts down the chip , disables the driver outputs, and pulls pwrgd low. 31 pwrgd power ? good output. open ? drain output. a low logic state means that the output voltage is outside of the vid dac defined range. 32 varfreq variable frequency enable input. pulling this pin to ground sets the normal rpm mode of operation. pulling this pin to 5.0 v sets the fixed ? frequency pwm mode of operation.
ADP3209D http://onsemi.com 4 electrical characteristics v cc = 5.0v, fbrtn = gnd, varfreq = low, v vid = 1.25 v, t a = ? 10 c to 100 c, unless otherwise noted (note 1). current entering a pi n (sunk by the device) has a positive sign. r ref = 80 k . parameter symbol conditions min typ max unit voltage control ? voltage error amplifier (veamp) fb, lline voltage range (note 2) v fb , v lline relative to csref = v dac ? 200 +200 mv fb, lline offset voltage (note 2) v osvea relative to csref = v dac ? 0.5 +0.5 mv fb bias current (note 2) i fb ? 1.0 +1.0 a lline bias current i ll ? 50 +50 na lline positioning accuracy v fb ? v vid measured on fb relative to v vid , lline forced 80 mv below csref ? 78 ? 80 ? 82 mv comp voltage range (note 2) v comp 0.85 4.0 v comp current i comp comp = 2.0 v, csref = v dac fb forced 200 mv below csref fb forced 200 mv above csref ? 0.75 3.0 ma comp slew rate sr comp c comp = 10 pf, csref = v dac , open loop configuration fb forced 200 mv below csref fb forced 200 mv above csref 15 ? 20 v/ s gain bandwidth (note 2) gbw non ? inverting unit gain configuration, r fb = 1 k 20 mhz vid dac voltage reference v dac voltage range (note 3) see vid code table 0 1.5 v v dac accuracy v fb ? v vid measured on fb (includes offset), relative to v vid , for vid table see table 1, t a = ? 10 c to 85 c ? 6.0 +6.0 mv v dac differential non ? linearity (note 2) ? 1.0 +1.0 lsb v dac line regulation v fb v cc = 4.75 v to 5.25 v 0.05 % soft ? start delay (note 2) t ss measured from en pos edge to fb = 1.25 v within 5% 1.8 ms v dac slew rate soft ? start non ? lsb vid step 0.0312 5.0 0.5 lsb/ s fbrtn current i fbrtn 70 200 a voltage monitoring and protection ? power good csref undervoltage threshold v uvcsref relative to nominal dac voltage ? 360 ? 300 ? 240 mv csref overvoltage threshold v ovcsref relative to nominal dac voltage 80 200 250 mv csref crowbar voltage threshold (note 2) v cbcsref relative to fbrtn 1.57 1.7 1.78 v csref reverse voltage threshold v rvcsref relative to fbrtn, latchoff mode: csref falling csref rising ? 350 ? 300 ? 75 ? 5.0 mv pwrgd low voltage v pwrgd i pwrgd(sink) = 4 ma 50 150 mv pwrgd high, leakage current i pwrgd v pwrdg = 5.0 v 0.1 a pwrgd startup delay t sspwrgd measured from en pos edge to pwrgd pos edge 2.0 ms 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. timing is referenced to the 90% and 10% points, unless otherwise noted.
ADP3209D http://onsemi.com 5 electrical characteristics v cc = 5.0v, fbrtn = gnd, varfreq = low, v vid = 1.25 v, t a = ? 10 c to 100 c, unless otherwise noted (note 1). current entering a pi n (sunk by the device) has a positive sign. r ref = 80 k . parameter unit max typ min conditions symbol voltage monitoring and protection ? power good pwrgd latchoff delay t loffpwrgd measured from out ? off ? good ? window event to latchoff (switching stops) 8.0 ms pwrgd propagation delay (note 3) t pdpwrgd measured from out ? off ? good ? window event to pwrgd neg edge 200 ns crowbar latchoff delay (note 2) t loffcb measured from crowbar event to latchoff (switching stops) 200 ns pwrgd masking time triggered by any vid change or ocp event 100 s csref soft ? stop resistance en = l or latchoff condition 70 current control ? current sense amplifier (csamp) cssum, csref common ? mode range (note 2) voltage range of interest 0 2.0 v cssum, csref offset voltage v oscsa csref ? cssum, t a = 25 c t a = ? 10 c to 85 c ? 0.5 ? 1.6 +0.5 +1.6 mv cssum bias current i bcssum ? 50 +50 na csref bias current i bcsref ? 2.0 +2.0 a cscomp voltage range (note 2) voltage range of interest 0.05 2.0 v cscomp current i cscompsource i cscompsink cscomp = 2.0 v cssum forced 200 mv below csref cssum forced 200 mv above csref ? 470 1.0 a ma cscomp slew rate c cscomp = 10 pf cssum forced 200 mv below csref cssum forced 200 mv above csref 10 ? 10 v/ s gain bandwidth (note 2) gbw csa non ? inverting unit gain configuration, r fb = 1 k 20 mhz current monitoring and protection current reference i ref voltage v ref r ref = 80 k to set i ref = 20 a 1.55 1.6 1.65 v current limiter (ocp) current limit threshold v limth measured from cscomp to csref, r lim = 4.5 k ? 70 ? 90 ? 11 0 mv current limit latchoff delay measured from ocp event to pwrgd de ? assertion 2.0 ms current monitor current gain accuracy i mon /i lim measured from i limp to i mon i lim = ? 20 a i lim = ? 10 a i lim = ? 5 a 9.4 9.2 9.0 10 10 10 10.7 11.0 11.3 i mon clamp voltage v maxmon relative to fbrtn 1.0 1.15 v pulse width modulator ? clock oscillator r t voltage v rt varfreq = low, r t = 120 k , v vid = 1.2500 v varfreq = high see also v rt (v vid ) formula 1.07 5.0 0.95 1.125 1.0 1.17 5.0 1.05 v pwm clock frequency range (note 2) f clk operation of interest 0.3 3.0 mhz pwm clock frequency f clk t a = +25 c, v vid = 1.2000 v r t = 73 k (note 2) r t = 125 k r t = 180 k (note 2) 970 705 500 1270 830 600 157 0 955 750 khz 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. timing is referenced to the 90% and 10% points, unless otherwise noted.
ADP3209D http://onsemi.com 6 electrical characteristics v cc = 5.0v, fbrtn = gnd, varfreq = low, v vid = 1.25 v, t a = ? 10 c to 100 c, unless otherwise noted (note 1). current entering a pi n (sunk by the device) has a positive sign. r ref = 80 k . parameter unit max typ min conditions symbol ramp generator ramp voltage v ramp en = high, i ramp = 30 a en = low 0.9 1.0 v in 1.1 v ramp current range (note 2) i ramp en = high en = low, ramp = 19 v 1.0 ? 0.1 100 +0.1 a pwm comparator pwm comparator offset (note 2) v osrpm v ramp ? v comp ? 3.0 +3.0 mv rpm comparator rpm current i rpm v vid = 1.2 v, r t = 180 k varfreq = low, see also i rpm (r t ) formula ? 6.0 a rpm comparator offset (note 2) v osrpm v comp ? (1 +v rpm ) ? 3.0 3.0 mv switch amplifier sw common mode range (note 2) v sw(x)cm operating range for current sensing ? 600 +200 mv sw resistance r sw(x) measured from sw to pgnd 1.5 k zero current switching comparator sw zcs threshold v dcm(sw1) ? 6.0 mv masked off time t offmskd measured from drvh neg edge to drvh pos edge at max frequency of operation 600 ns system i/o buffers vid[4:0] inputs input voltage refers to driving signal level: logic low, i sink 1 a logic high, i source ? 5 a 1.7 0.3 v input current v = 0.2 v, vid[4:0] (active pulldown to gnd) ? 1.0 a vid delay t ime (note 2) any vid edge to fb change 10% 200 ns varfreq input voltage refers to driving signal level: logic low, i sink 1 a logic high, i source ? 5 a 4.0 0.3 v input current ? 1.0 a en input input voltage refers to driving signal level: logic low, i sink 1 a logic high, i source ? 5 a 1.6 0.3 v input current en = l or en = h (static) 0.8 v < en < 1.6 v (during transition) 10 70 na a supply supply voltage range v cc 4.5 5.5 v supply current en = h en = 0 v 5.0 60 8.0 150 ma a v cc ok threshold v ccok v cc is rising 4.4 4.5 v v cc uvlo threshold v ccuvlo v cc is falling 4.0 4.15 v v cc hysteresis (note 2) 250 mv 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. timing is referenced to the 90% and 10% points, unless otherwise noted.
ADP3209D http://onsemi.com 7 electrical characteristics v cc = 5.0v, fbrtn = gnd, varfreq = low, v vid = 1.25 v, t a = ? 10 c to 100 c, unless otherwise noted (note 1). current entering a pi n (sunk by the device) has a positive sign. r ref = 80 k . parameter unit max typ min conditions symbol high ? side mosfet driver pullup resistance, sourcing current bst = pvcc 1.8 3.3 pulldown resistance, sinking current bst = pvcc 1.0 3.0 transition times tr drvh tf drvh bst = pvcc, c l = 3 nf, figure 2 bst = pvcc, c l = 3 nf, figure 2 15 13 35 31 ns dead delay times tpdh drvh bst = pvcc, figure 2 30 42 ns bst quiescent current en = l (shutdown) en = h, no switching 2.0 200 12 a low ? side mosfet driver pullup resistance, sourcing current bst = pvcc 1.7 3.3 pulldown resistance, sinking current bst = pvcc 0.8 2.0 transition times tr drvl tf drvl c l = 3 nf, figure 2 c l = 3 nf, figure 2 15 14 35 35 ns progation delay times tpdh drvl c l = 3 nf, figure 2 10 30 ns sw transition timeout t tosw drvh = l, sw = 2.5 v 150 250 350 ns sw off threshold v offsw 1.6 v pvcc quiescent current en = l (shutdown) en = h, no switching 5.0 240 15 a bootstrap rectifier switch on resistance en = l or en = h and drvl = h 3.0 6.0 1.0 1. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2. guaranteed by design or bench characterization, not production tested. 3. timing is referenced to the 90% and 10% points, unless otherwise noted. figure 2. timing diagram (note 3) in drvh (with respect to sw) drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1.0 v tpdh drvl
ADP3209D http://onsemi.com 8 typical performance characteristics v vid = 1.5 v, t a = 20 c to 100 c, unless otherwise noted. figure 3. switching frequency vs. load current in rpm mode figure 4. switching frequency vs. input voltage in rpm mode figure 5. switching frequency vs. input voltage in rpm mode figure 6. load line accuracy figure 7. dcm waveforms, 0.5 a load current figure 8. ccm waveforms, 3 a load current 100 150 200 250 300 350 400 450 0.25 0.5 0.75 1 1.25 1.5 output voltage (v) switching frequency (khz) 20 30 40 50 60 70 80 90 output ripple (mv) input = 12 v load = 10 a output ripple switching frequency 350 375 400 425 450 5101520 input voltage (khz) switching frequency (khz) 0 10 20 30 40 output ripple (mv) output = 1.2 v load = 10 a switching frequency output ripple 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 051015 load current (a) output voltage (v) +2% ? 2% measured load line switch node low side gate output voltage inductor current low side gate output voltage inductor current switch node
ADP3209D http://onsemi.com 9 typical performance characteristics v vid = 1.5 v, t a = 20 c to 100 c, unless otherwise noted. figure 9. load transient, 3 a to 10 a, v in = 12 v figure 10. load transient, 3 a to 10 a, v in = 12 v figure 11. load transient, 3 a to 10 a, v in = 12 v figure 12. vid otf, 1.25 v to 0.85 v switch node output voltage output voltage switch node output voltage vid0 output voltage
ADP3209D http://onsemi.com 10 theory of operation the ADP3209D is a ramp ? pulse ? modulated (rpm) controller for synchronous buck intel gmch core power supply. the internal 5 ? bit vid dac conforms to the intel imvp ? 6+ specifications. the ADP3209D is a stable, high performance architecture that includes ? high speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors ? minimized thermal switching losses due to lower frequency operation ? high accuracy load line regulation ? high power conversion efficiency with a light load by automatically switching to dcm operation operation modes the ADP3209D runs in rpm mode for the purpose of fast transient response and high light load ef ficiency. during the following transients, the ADP3209D runs in pwm mode: ? soft ? start ? soft transient: the period of 100 s following any vid change ? current overload figure 13. rpm mode operation i r = a r i ramp q s rd flip ? flop q s rd flip ? flop r a c fb r b c a c b vdc v cs r cs c cs r ph drvh drvl gate driver sw vcc l r i load comp fb fbrtn cscomp cssum csref drvl1 sw1 drvh1 c r vrmp bst bst1 5.0 v q 400 ns q r2 r1 r1 r2 1.0 v 30 mv in dcm lline + ? + ? + + 1.0 v 1.0 v
ADP3209D http://onsemi.com 11 figure 14. pwm mode operation i r = a r i ramp a d clock oscillator q s rd flip ? flop vcc l r i load c r drvh drvl gate driver sw vcc drvl1 sw1 drvh1 bst bst1 5.0 v in ramp r a c fb r b c a c b vdc v cs r cs c cs r ph comp fb fbrtn cscomp cssum csref lline + + ? + ? + 0.2 v setting switch frequency master clock frequency in pwm mode when the ADP3209D runs in pwm, the clock frequency is set by an external resistor connected from the rt pin to gnd. the frequency varies with the vid voltage: the lower the vid voltage, the lower the clock frequency. the variation of clock frequency with vid voltage maintains constant v cgfx ripple and improves power conversion efficiency at lower vid voltages. switching frequency in rpm mode when the ADP3209D operates in rpm mode, its switching frequency is controlled by th e ripple voltage on the comp pin. each time the comp pin voltage exceeds the rpm pin voltage threshold level determ ined by the vid voltage and the external resistor connect ed between rpm and gnd, an internal ramp signal is started and drvh is driven high. the slew rate of the internal ra mp is programmed by the current entering the ramp pin. one ? third of the ramp current charges an internal ramp capacitor (5 pf typical) and creates a ramp. when the internal ramp signal intercepts the comp voltage, the drvh pin is reset low. in continuous current mode, the switching frequency of rpm operation is almost constant. while in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. differential sensing of output voltage the ADP3209D combines differential sensing with a high accuracy vid dac, referenced by a precision band gap source and a low of fset error amplifier, to meet the rigorous accuracy requirement of the intel imvp ? 6+ specification. in steady ? state mode, the combination of the vid dac and error amplifier maintain the output voltage for a worst ? case scenario within 8 mv of the full operating output voltage and temperature range. the v ccgfx output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the positive regulation point; the vcc remote sensing pin of the gmch. fbrtn should be connected directly to the negative remote sensing point; the v ss sensing point of the gmch. the internal vid dac and precision voltage reference are referenced to fb rtn and have a typical current of 200 a for guaranteed accu rate remote sensing. output current sensing the ADP3209D includes a dedicated current sense amplifier (csa) to monitor the total output current of the converter for proper voltage positioning vs. load current and for overcurrent detection. sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low ? side mosfet. the current sense
ADP3209D http://onsemi.com 12 amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by: ? output inductor esr sensing without the use of a thermistor for the lowest cost ? output inductor esr sensing with the use of a thermistor that tracks inductor temperature to improve accuracy ? discrete resistor sensing for the highest accuracy at the positive input of the csa, the csref pin is connected to the output voltage. at the negative input (that is, the csfb pin of the csa), signals from the sensing element (in the case of inductor dcr sensing, signals from the switch node side of the output inductors) are connected with a resistor. the feedback resistor between the cscomp and csfb pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. the current information is then given as the voltage difference between the cscomp and csref pins. this signal is used internally as a dif ferential input for the current limit comparator. an additional resistor divider connected between the cscomp and csref pins with the midpoint connected to the lline pin can be used to set the load line required by the gmch specification. the current information to set the load line is then given as the voltage dif ference between the lline and csref pins. this configuration allows the load line slope to be set independent from the current limit threshold. if the current limit threshold and load line do not have to be set independently, the resistor divider between the cscomp and csref pins can be omitted and the cscomp pin can be connected directly to lline. to disable voltage positioning entirely (that is, to set no load line), lline should be tied to csref. to provide the best accuracy for current sensing, the csa has a low offset input voltage and the sensing gain is set by an external resistor ratio. active impedance control mode to control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between lline and csref, can be scaled to be equal to the required droop voltage. this droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. this value is used as the control voltage of the pwm regulator. the droop voltage is subtracted from the dac reference output voltage, and the resulting voltage is used as the voltage positioning set ? point. the arrangement results in an enhanced feed ? forward response. voltage control mode a high ? gain bandwidth error amplifier is used for the voltage mode control loop. the non ? inverting input voltage is set via the 5 ? bit vid dac. the vid codes are listed in table 1. the non ? inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. the output of the error amplifier is the comp pin, which sets the termination voltage of the internal pwm ramps. at the negative input, the fb pin is tied to the output sense location us ing r b , a resistor for sensing and controlling the output voltage at the remote sensing point. the main loop compensation is incorporated in the feedback network connected between the fb and comp pins. power ? good monitoring the power ? good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open ? drain output that can be pulled up through an external resistor to a voltage rail; not necessarily the same vcc voltage rail that is running the controller. a logic high level indicates that the output voltage is within the voltage limits defined by a range around the vid voltage setting. pwrgd goes low when the output voltage is outside of this range. following the gmch specification, the pwrgd range is defined to be 300 mv less than and 200 mv greater than the actual vid dac output voltage. to prevent a false alarm, the power ? good circuit is masked during any vid change and during soft ? start. the duration of the pwrgd mask is set to approximately 100 s by an internal timer. power ? up sequence and soft start the power ? on ramp ? up time of the output voltage is set internally. the ADP3209D steps sequentially through each vid code until it reaches the set vid code voltage. the power ? up sequence, including the soft ? start is illustrated in figure 15. figure 15. powerup sequence of ADP3209D v5_s gfxcore_en vccgfx pwrgd pgdelay 100 mv/ s vid change and soft transient when a vid input changes, the ADP3209D detects the change but ignores new code for a minimum of 400 ns. this delay is required to prevent the device from reacting to digital signal skew while the 5 ? bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failu re. each vid change resets and retriggers the internal pwrgd masking timer.
ADP3209D http://onsemi.com 13 the ADP3209D provides a soft transient function to reduce inrush current during vid transitions. reducing the inrush current helps decrease the acoustic noise generated by the mlcc input capacitors and inductors. the soft transient feature is implemented internally. when a new vid code is detected, the ADP3209D steps sequentially through each vid voltage to the final vid voltage. the ADP3209D steps through vid codes every 0.5 s. this gives a soft transient slew rate of 25 mv per 0.5 s or 12.5 mv/ s. there is a pwrgd masking time of 100 s after the last vid code is changed internally. current limit, short ? circuit, and latchoff protection the ADP3209D has an adjustable current limit set by the r clim resistor. this resistor is connected from the ilimn to ilimp. normally, the ADP3209D operates in rpm mode. during a current overload, the ADP3209D switches to pwm mode. with low impedance loads, the ADP3209D operates in a constant current mode to ensure that the external mosfets and inductor function properly and to protect the gpu. with a low constant impedance load, the output voltage decreases to supply only the set current limit. if the output voltage drops below the power ? good limit, the pwrgd signal transitions. after the pwrgd single transitions, the ADP3209D will latchoff after 9 ms. the latchoff function can be reset either by removing and reapplying vcc or by briefly pulling the en pin low. during startup, when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the voltage swing of cscomp cannot extend below ground. this secondary current limit clamp controls the minimum internal comp voltage to the pwm comparators to 1.5 v. this limits the voltage drop across the low ? side mosfets through the current balance circuitry. light load rpm dcm operation the ADP3209D operates in rpm mode. with higher loads, the ADP3209D operates in continuous conduction mode (ccm), and the upper and lower mosfets run synchronously and in complementary phase. see figure 16 for the typical waveforms of the ADP3209D running in ccm with a 7 a load current. figure 16. single ? phase waveforms in ccm 3 1 2 4 400 ns/div output voltage 20 mv/div inductor current 5 a/div switch node 5.0 v/div low ? side gate 5.0 v/div with lighter loads, the ADP3209D enters discontinuous conduction mode (dcm). figure no tag shows a typical single ? phase buck with one upper fet, one lower fet, an output inductor, an output capacitor, and a load resistor. figure 18 shows the path of the inductor current with the upper fet on and the lower fet off. in figure 19 the high ? side fet is off and the low ? side fet is on. in ccm, if one fet is on, its complementary fet must be off; however, in dcm, both high ? and low ? side fets are off and no current flows into the inductor (see figure 20). figure 21 shows the inductor current and switch node voltage in dcm. in dcm with a light load, the ADP3209D monitors the switch node voltage to determine when to turn off the low ? side fet. figure 22 shows a typical waveform in dcm with a 1 a load current. between t 1 and t 2 , the inductor current ramps down. the current flows through the source drain of the low ? side fet and creates a voltage drop across the fet with a slightly negative switch node. as the inductor current ramps down to 0 a, the switch voltage approaches 0 v, as seen just before t 2 . when the switch voltage is approximately ? 6 mv, the low ? side fet is turned off. figure 21 shows a small, dampened ringing at t 2 . this is caused by the lc created from capacitance on the switch node, including the c ds of the fets and the output inductor. this ringing is normal. the ADP3209D automatically goes into dcm with a light load. figure 22 shows the typical dcm waveform of the ADP3209D with a 1 a load current. as the load increases, the ADP3209D enters into ccm. in dcm, frequency decreases with load current, and switching frequency is a function of the inductor, load current, input voltage, and output voltage. figure 17. buck topology switch node l drvl drvh q1 q2 c output voltage load input voltage figure 18. buck topology inductor current during t 0 and t 1 l c on off load
ADP3209D http://onsemi.com 14 figure 19. buck topology inductor current during t 1 and t 2 l c on off load figure 20. buck topology inductor current during t 2 and t 3 l c off off load fi g ure 21. inductor current and switch node in dcm inductor current switch node voltage t 0 t 1 t 2 t 3 t 4 figure 22. single ? phase waveforms in dcm with 1 a load current 3 1 2 4 2 s/div switch node 5.0 v/div low ? side gate drive 5.0 v/div output voltage 20 mv/div inductor current 5 a/div output crowbar to protect the load and output components of the supply, the drvl output is driven high (turning the low ? side mosfets on) and drvh is driven low (turning the high ? side mosfets off) when the output voltage exceeds the gmch ovp threshold. turning on the low ? side mosfets forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. if the output overvoltage is due to a drain ? source short of the high ? side mosfet, turning on the low ? side mosfet results in a crowbar across the input voltage rail. the crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the gmch chipset from destruction. when the ovp feature is triggered, the ADP3209D is latched off. the latchoff function can be reset by removing and reapplying vcc to the ADP3209D or by briefly pulling the en pin low. reverse voltage protection very large reverse current in inductors can cause negative v ccgfx voltage, which is harmful to the chipset and other output components. the ADP3209D provides a reverse voltage protection (rvp) function without additional system cost. the v ccgfx voltage is monitored through the csref pin. when the csref pin voltage drops to less than ? 300 mv, the ADP3209D triggers the rvp function by setting both drvh and drvl low, thus turning off all mosfets. the reverse inductor currents can be quickly reset to 0 by discharging the built ? up energy in the inductor into the input dc voltage source via the forward ? biased body diode of the high ? side mosfets. the rvp function is terminated when the csref pin voltage returns to greater than ? 100 mv. sometimes the crowbar feature inadvertently results in negative v ccgfx voltage because turning on the low ? side mosfets results in a very large reverse inductor current. to prevent damage to the chipset caused from negative voltage, the ADP3209D maintains its rvp monitoring function even after ovp latchoff. during ovp latchoff, if the csref pin voltage drops to less than ? 300 mv, the low ? side mosfets is turned off by setting drvl low. drvl will be set high again when the csref voltage recovers to greater than ? 100 mv. figure 23 shows the reverse voltage protection function of the ADP3209D. the csref pin is disconnected from the output voltage and pulled negative. as the csref pin drops to less than ? 300 mv, the low ? side and high ? side fets turn off.
ADP3209D http://onsemi.com 15 fi g ure 23. ADP3209D rvp function ch1 5.00v ch3 1.00v ch2 5.00v ch4 20.0v m2.00 s a ch3 580mv 3 4 2 1 csref pwrgd drvh drvl output enable and uvlo for the ADP3209D to begin switching, the vcc supply voltage to the controller mu st be greater than the v ccok threshold and the en pin must be driven high. if the vcc voltage is less than the v ccuvlo threshold or the en pin is logic low, the ADP3209D shuts off. in shutdown mode, the controller holds drvh and drvl low, shorts the capacitors of the ss and pgdelay pins to ground, and drives pwrgd to low. the user must adhere to proper power ? supply sequencing during startup and shutdown of the ADP3209D. all input pins must be at ground prior to removing or applying vcc, and all output pins should be left in high impedance state while vcc is off. current monitor function the ADP3209D has an output current monitor. the imon pin sources a current proportional to the inductor current. a resistor from imon pin to fbrtn sets the gain. a 0.1 f is added in parallel with r mon to filter the inductor ripple. the imon pin is clamped to prevent it from going above 1.15 v. table 1. vid code table enable vid4 vid3 vid2 vid1 vid0 nominal v ccgfx (v) 1 0 0 0 0 0 1.250 1 0 0 0 0 1 1.225 1 0 0 0 1 0 1.200 1 0 0 0 1 1 1.175 1 0 0 1 0 0 1.150 1 0 0 1 0 1 1.125 1 0 0 1 1 0 1.100 1 0 0 1 1 1 1.075 1 0 1 0 0 0 1.050 1 0 1 0 0 1 1.025 1 0 1 0 1 0 1.000 1 0 1 0 1 1 0.975 1 0 1 1 0 0 0.950 1 0 1 1 0 1 0.925 1 0 1 1 1 0 0.900 1 0 1 1 1 1 0.875 1 1 0 0 0 0 0.850 1 1 0 0 0 1 0.825 1 1 0 0 1 0 0.800 1 1 0 0 1 1 0.775 1 1 0 1 0 0 0.750 1 1 0 1 0 1 0.725 1 1 0 1 1 0 0.700 1 1 0 1 1 1 0.675 1 1 1 0 0 0 0.650 1 1 1 0 0 1 0.625 1 1 1 0 1 0 0.600 1 1 1 0 1 1 0.575 1 1 1 1 0 0 0.550 1 1 1 1 0 1 0.525 1 1 1 1 1 0 0.500 1 1 1 1 1 1 0.400 0 x x x x x 0.000
ADP3209D http://onsemi.com 16 figure 24. typical application circuit vid4 vid3 vid2 vid1 vid0 fbrtn fb nc nc imon iref rpm vcc bst drvh sw pvcc drvl pgnd e n i l l p m o c s c f e r s c p m a r n m i l i p m i l i t r 32 adp3209 d b f s c 1 comp gnd vr_on v5s r16 dnp r19 0 pwrgd r1 10k r2 10 c6 1 f rb1 1% cb1, dnp ra1 20.0k 1% ca1, 470pf cfb1 22pf tp3 comp r3 33.2k 1% c28 1nf r53, 100 tp5 fb tp6 fbrtn r13, 100 vccsense vsssense r17 0 c8 4.7 f jp1 shortpin q2 ntmfs4846n q1 ntmfs4821n q3 ntmfs4846n c1 10 f 25v c2 10 f 25v c3 10 f 25v c4 10 f 25v vdc 560nh/1.3m c21 gnd vdc gnd rth1 8% ntc rcs1 76.8k , 1% ccs1 dnp ccs2 2.2nf rcs2 140k , 1% tp7 con2 1 2 r9 dnp r7 200k r8 357k c25 1nf r11 340k r12 1.00k 1% c27 100pf vdc r10 0 r4 dnp c24 dnp rph1 59.0k 1% rph2 tp8 sw tp11 drvh rs1 (optional) r55 0 r54 (optional) vgfx_core vgfx_core_rtn tp12 drvl c9 22 f 6.3v c10 22 f 6.3v c11 0.22 f c12 0.1 f c13 0.1 f c14 1nf c15 dnp vgfx_core_rtn c22 220 f 2.5v c23 220 f 2.5v c30 dnp c31 dnp vgfx_core vgfx_core v5s connect power ground to controller ground under the controller. v3.3s q e r f r a v d g r w p n e 0 d i v 1 d i v 2 d i v 3 d i v 4 d i v 1.00k tp10 imon rimon ?% ??? r14 ?% ??? r18 ?% ??? 1% dnp 1 f l1 c?? 0.1 f 220k
ADP3209D http://onsemi.com 17 application information the design parameters for a typical imvp ? 6+ compliant gpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 8.0 v ? output voltage by vid setting (v vid ) = 1.25 v ? maximum output current (i o ) = 15 a ? droop resistance (r o ) = 5.1 m ? nominal output voltage at 15 a load (v ofl ) = 1.174 v ? static output voltage drop from no load to full load ( v) = v onl ? v ofl = 1.25 v ? 1.174 v = 76 mv ? maximum output current step ( i o ) = 8 a ? number of phases (n) = 1 ? switching frequency (f sw ) = 390 khz ? duty cycle at maximum input voltage (d max ) = 0.15 v ? duty cycle at minimum input voltage (d min ) = 0.062 v setting the clock frequency for pwm in pwm operation, the ADP3209D uses a fixed ? frequency control architecture. the frequency is set by an external timing resistor (rt). the clock frequency determines the switching frequency, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. for example, a clock frequency of 300 khz sets the switching frequency to 300 khz. this selection represents the trade ? off between the switching losses and the minimum sizes of the output filter components. to achieve a 300 khz oscillator frequency at a vid voltage of 1.2 v, rt must be 237 k . alternatively, the value for rt can be calculated by using the following equation: r t v vid 1.0 v 2 f sw 9pf 16 k (eq. 1) where: 9 pf and 16 k are internal ic component values. v vid is the vid voltage in volts. f sw is the switching frequency in hertz. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. with varfreq pulled above 4.0 v, the ADP3209D operates with a constant switching frequency. the switching frequency does not change with vid voltage, input voltage, or load current. in addition, the dcm operation at light load is disabled, so the ADP3209D operates in ccm. the value of rt can be calculated by using the following equation: r t 1.0 v f sw 9pf 16 k (eq. 2) ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use this equation to determine a starting value: r r a r l 3 a d r ds c r r r 0.5 360 nh 3 5 5.2 m 5pf 462 k (eq. 3) where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low ? side mosfet on ? resistance, c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 3). for stability and noise immunity, keep this ramp size larger than 0.5 v. t aking this into consideration, the value of r r is selected as 280 k . the internal ramp voltage magnitude can be calculated using: v r a r (1 d) v vid r r c r f sw v r 0.5 (1 0.061) 1.150 v 462 k 5pf 280 khz 0.83 v (eq. 4) the size of the internal ramp can be made larger or smaller. if it is made larger, then stability and transient response improves, but thermal balance degrades. likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. the factor of three in the denominator of equation 4 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance. setting the switching frequency for rpm operation during the rpm operation, the ADP3209D runs in pseudo ? constant frequency if the load current is high enough for continuous current mode. while in dcm, the switching frequency is reduced with the load current in a linear manner. to save power with light loads, lower switching frequency is usually preferred during rpm operation. however, the v ccgfx ripple specification of imvp ? 6+ sets a limitation for the lowest switching frequency. therefore, depending on the inductor and output capacitors, the switching frequency in rpm can be equal to, greater than, or less than its counterpart in pwm. a resistor from rpm to gnd sets the pseudo constant frequency as following: r rpm 2 r t v vid 1.0 v a r ( 1 d ) v vid r r c r f sw 0.5 k (eq. 5) where: a r is the internal ramp amplifier gain. c r is the internal ramp capacitor value. r r is an external resistor on the rampadj pin to set the internal ramp magnitude.
ADP3209D http://onsemi.com 18 because r r = 280 k , the following resistance sets up 300 khz switching frequency in rpm operation. r rpm 2 280 k 1.150 v 1.0 v 0.5 ( 1 0.061 ) 1.150 462 k 5pf 300 khz (eq. 6) 500 k 202 k inductor selection the choice of inductance determines the ripple current of the inductor. less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the mosfets. however, this allows the use of smaller ? size inductors, and for a specified peak ? to ? peak transient deviation, it allows less total output capacitance. conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger ? size inductors and more output capacitance for the same peak ? to ? peak transient deviation. for a buck converter, the practical value for peak ? to ? peak inductor ripple current is less than 50% of the maximum dc current of that inductor. equation 7 shows the relationship between the inductance, oscillator frequency, and peak ? to ? peak ripple current. equation 8 can be used to determine the minimum inductance based on a given output ripple voltage. i r v vid 1 d min f sw l (eq. 7) l v vid r o (1 (n d min)) f sw v ripple (eq. 8) in this example, r o is assumed to be the esr of the output capacitance, which results in an optimal transient response. solving equation 9 for a 16 mv peak ? to ? peak output ripple voltage yields: l 1.174 v 5.1 m (1 0.062) 390 khz 16 mv 901 nh (eq. 9) if the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. this iteration allows optimal transient response and minimum output decoupling. in this example, the iteration showed that a 560 nh inductor was sufficient to achieve a good ripple. the smallest possible inductor should be used to minimize the number of output capacitors. choosing a 560 nh inductor is a good choice for a starting point, and it provides a calculated ripple current of 6.6 a. the inductor should not saturate at the peak current of 18.3 a, and it should be able to handle the sum of the power dissipation caused by the winding?s average current (15 a) plus the ac core loss. another important factor in the inductor design is the dcr, which is used for measuring the inductor current. too large of a dcr causes excessive power losses, whereas too small of a value leads to increased measurement error. for this example, an inductor with a dcr of 1.3 m is used. selecting a standard inductor after the inductance and dcr are known, select a standard inductor that best meets the overall design goals. it is also important to specify the inductance and dcr tolerance to maintain the accuracy of the system. using 20% tolerance for the inductance and 15% for the dcr at room temperature are reasonable values that most manufacturers can meet. power inductor manufacturers the following companies provide surface ? mount power inductors optimized for high power applications upon request. ? vishay dale electronics, inc. ? panasonic ? sumida electric company ? nec tokin corporation output droop resistance the design requires that the regulator output voltage measured at the chipset pins decreases when the output current increases. the specified voltage drop corresponds to the droop resistance (r o ). the output current is measured by low ? pass filtering the voltage across the inductor or current sense resistor. the filter is implemented by the cs amplifier that is configured with r ph , r cs , and c cs . the output resistance of the regulator is set by the following equations: r o r cs r ph(x) r sense (eq. 10) c cs l r sense r cs (eq. 11) where r sense is the dcr of the output inductors. either r cs or r ph can be chosen for added flexibility. due to the current drive ability of the cscomp pin, the r cs resistance should be greater than 100 k . for example, initially select r cs to be equal to 200 k , and then use equation 11 to solve for c cs : c cs 560 nh 1.3 m 200 k 2.2 nf (eq. 12) if c cs is not a standard capacitance, r cs can be tuned. in this case, the required c cs is a standard value and no tuning is required. for best accuracy, c cs should be a 5% npo capacitor. next, solve for r ph by rearranging equation 10 as follows: (eq. 13) r ph 1.3 m 5.1 m 200 k 51.0 k the standard 1% resistor for r ph is 51.1 k .
ADP3209D http://onsemi.com 19 inductor dcr temperature correction if the dcr of the inductor is used as a sense element and copper wire is the source of the dcr, the temperature changes associated with the inductor?s winding must be compensated for. fortunately, copper has a well ? known temperature coefficient (tc) of 0.39%/ c. if r cs is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor?s dcr. due to the nonlinear nature of ntc thermistors, series resistors r cs1 and r cs2 (see figure 25) are needed to linearize the ntc and produce the desired temperature coefficient tracking. figure 25. temperature ? compensation circuit values c cs1 c cs2 cscomp csfb csref r cs1 r cs2 adp3209 to switch node r ph place as close as possible to inductor or low-side mosfet 10 12 11 keep this path as short as possible and away from to v ccgfx sense r th switch node lines the following procedure and expressions yield values for r cs1 , r cs2 , and r th (the thermistor value at 25 c) for a given r cs value. 1. select an ntc to be used based on its type and value. because the value needed is not yet determined, start with a thermistor with a value close to r cs and an ntc with an initial tolerance of better than 5%. 2. find the relative resistance value of the ntc at two temperatures. the appropriate temperatures will depend on the type of ntc, but 50 c and 90 c have been shown to work well for most types of ntcs. the resistance values are called a (a is r th (50 c)/r th (25 c)) and b (b is r th (90 c)/r th (25 c)). note that the relative value of the ntc is always 1 at 25 c. 3. find the relative value of r cs required for each of the two temperatures. the relative value of r cs is based on the percentage of change needed, which is initially assumed to be 0.39%/ c in this example. the relative values are called r 1 (r 1 is 1/(1+ tc (t 1 ? 25))) and r 2 (r 2 is 1/(1 + tc (t 2 ? 25))), where tc is 0.0039, t 1 is 50 c, and t 2 is 90 c. 4. compute the relative values for r cs1 , r cs2 , and r th by using the following equations: (a b) r 1 r 2 a (1 b) r 2 b (1 a) r 1 a (1 b) r 1 b (1 a) r 2 (a b) r cs2 (eq. 14) r th 1 1 1 r cs2 1 r cs1 r cs1 (1 a) 1 1 r cs2 1 r 1 r cs2 5. calculate r th = r th r cs , and then select a thermistor of the closest value available. in addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k r th(actual) r th(calculated) (eq. 15) 6. calculate values for r cs1 and r cs2 by using the following equations: r cs1 r cs k r cs1 (eq. 16) r cs2 r cs ((1 k) (k r cs2 )) for example, if a thermistor value of 100 k is selected in step 1, an available 0603 ? size thermistor with a value close to r cs is the v ishay nths0603n04 ntc thermistor, which has resistance values of a = 0.3359 and b = 0.0771. using the equations in step 4, r cs1 is 0.359, r cs2 is 0.729, and r th is 1.094. solving for r th yields 219 k , so a thermistor of 220 k would be a reasonable selection, making k equal to 1.005. finally, r cs1 and r cs2 are found to be 72.2 k and 146 k . choosing the closest 1% resistor values yields a choice of 71.5 k and 147 k . c out selection the required output decoupling for processors and platforms is typically recommended by intel. for systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. select the number of ceramics and determine the total ceramic capacitance (c z ). this is based on the number and type of capacitors used. keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805 ? size pieces inside the socket. additional ceramic capacitors can be placed along the outer edge of the socket. a combined ceramic capacitor value of 40 f to 50 f is recommended and is usually composed of multiple 10 f or 22 f capacitors. ensure that the total amount of bulk capacitance (c x ) is within its limits. the upper limit is dependent on the vid otf output voltage stepping (voltage step, v v , in time, t v , with error of v err ); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, i o . the current version of the imvp ? 6+ specification allows a maximum v ccgfx overshoot (v osmax ) of 10 mv more than the vid voltage for a step ? off load current.
ADP3209D http://onsemi.com 20 c x(min)
l i o r o v osmax i o v vid c z
(eq. 17) c x(max) l k 2 r o 2 v v v vid
1 t v v vid v v k r o l 2 1
c z where: k ? 1n v err v v (eq. 18) to meet the conditions of these expressions and the transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is greater than c x(max) , the system does not meet the vid otf specifications and may require less inductance. in addition, the switching frequency may have to be increased to maintain the output ripple. for example, if two pieces of 22 f, 0805 ? size mlc capacitors (c z = 44 f) are used during a vid voltage change, the v ccgfx change is 220 mv in 22 s with a setting error of 10 mv. if k = 3.1, solving for the bulk capacitance yields: c x(min)
560 nh 8a 5.1 m 10 mv 8a 1.174 v 44 f
256 f c x(max) 560 nh 220 mv 3.1 2 (5.1 m ) 2 1.174 v
1 22 s 1.174 v 3.1 5.1 m 220 mv 560 nh 2 1
992 f using two 220 f panasonic sp capacitors with a typical esr of 7 m each yields c x = 440 f and r x = 3.5 m . ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using: l x 44 f (5.1 m ) 2 2 2.3 nh (eq. 19) l x c z r o 2 q 2 where: q is limited to the square root of 2 to ensure a critically damped system. l x is about 450 ph for the two sp capacitors, which is low enough to avoid ringing during a load change. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. for this multi ? mode control technique, an all ceramic capacitor design can be used if the conditions of equations 17, 18, and 19 are satisfied. power mosfets for typical 15 a per phase applications, the n ? channel power mosfets are selected for one high ? side switch and one low ? side switch. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . because the voltage of the gate driver is 5.0 v, logic ? level threshold mosfets must be used. the maximum output current, i o , determines the r ds(on) requirement for the low ? side (synchronous) mosfets. with conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and the average total output current (i o ): p sf (1 d) i o n sf 2 1 12 i r n sf 2 r ds(sf) (eq. 20) where: d is the duty cycle and is approximately the output voltage divided by the input voltage. i r is the inductor peak ? to ? peak ripple current and is approximately: i r ( 1 d ) v out l f sw (eq. 21) knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required r ds(on) for the mosfet. for an 8 ? lead soic or 8 ? lead soic ? compatible mosfet, the junction ? to ? ambient (pcb) thermal impedance is 50 c/w. in the worst case, the pcb temperature is 70 c to 80 c during heavy load operation of the notebook, and a safe limit for p sf is about 0.8 w to 1.0 w at 120 c junction temperature. ther efore, for this example (15 a maximum), the r ds(sf) per mosfet is less than 18.8 m for the low ? side mosfet. this r ds(sf) is also at a junction temperature of about 120 c; therefore, the r ds(sf) per mosfet should be less than 13.3 m at room temperature, or 18.8 m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous mosfets when the switch node goes high. the high ? side (main) mosfet must be able to handle two main power dissipation components: conduction losses and switching losses. switching loss is related to the time for the main mosfet to turn on and off and to the current and voltage that are being switched. basing the switching speed on the rise and fall times of the gate driver impedance and mosfet input capacitance, the following expression
ADP3209D http://onsemi.com 21 provides an approximate value for the switching loss per main mosfet: p s(mf) 2 f sw v dc i o n mf r g n mf c iss (eq. 22) where: n mf is the total number of main mosfets. r g is the total gate resistance. c iss is the input capacitance of the main mosfet. the most effective way to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the following equation: p c(mf) d i o n mf 2 1 12 i r n mf 2 r ds(mf) (eq. 23) where r ds(mf) is the on resistance of the mosfet. typically, a user wants the highest speed (low c iss ) device for a main mosfet, but such a device usually has higher on resistance. therefore, the user must select a device that meets the total power dissipation (about 0.8 w to 1.0 w for an 8 ? lead soic) when combining the switching and conduction losses. for example, an irf7821 device can be selected as the main mosfet (one in total; that is, n mf = 1), with approximately c iss = 1010 pf (maximum) and r ds(mf) = 18 m (maximum at t j = 120 c), and an ir7832 device can be selected as the synchronous mosfet (two in total; that is, n sf = 2), with r ds(sf) = 6.7 m (maximum at t j = 120 c). solving for the power dissipation per mosfet at i o = 15 a and i r = 5.0 a yields 178 mw for each synchronous mosfet and 446 mw for each main mosfet. a third synchronous mosfet is an option to further increase the conversion efficiency and reduce thermal stress. finally, consider the power dissipation in the driver. this is best described in terms of the q g for the mosfets and is given by the following equation: p drv (eq. 24) f sw 2 n n mf q gmf n sf q gsf i cc v cc where q gmf is the total gate charge for each main mosfet, and q gsf is the total gate charge for each synchronous mosfet. the previous equation also shows the standby dissipation (i cc times the vcc) of the driver. ramp resistor selection the ramp resistor (r r ) is used to set the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of stability and transient response. use the following expression to determine a starting value: r r a r l 3 a d r ds c r r r 0.2 560 nh 3 5 3.4 m 5pf 439 k (eq. 25) where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low ? side mosfet on resistance. c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 26). for stability and noise immunity, keep the ramp size larger than 0.5 v. t aking this into consideration, the value of r r in this example is selected as 340 k . the internal ramp voltage magnitude can be calculated as follows: v r a r (1 d) v vid r r c r f sw v r 0.2 (1 0.062) 1.174 v 340 k 5pf 390 khz 0.33 v (eq. 26) the size of the internal ramp can be increased or decreased. if it is increased, stability and transient response improves but thermal balance degrades. conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. in the denominator of equation 25, the factor of 3 sets the minimum ramp size that produces an optimal balance of good stability and transient response. comp pin ramp in addition to the internal ramp, there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input: v rt v r 1 2 (1 d) f sw c x r o (eq. 27) where c x is the total bulk capacitance, and r o is the droop resistance of the regulator. for this example, the overall ramp signal is 0.23 v. current limit setpoint to select the current limit setpoint, we need to find the resistor value for r lim . the current limit threshold for the ADP3209D is set when the current in r lim is equal to the internal reference current of 20 a. the current in r lim is equal to the inductor current times r o . r lim can be found using the following equation: r lim i lim r o 20 a (eq. 28)
ADP3209D http://onsemi.com 22 where: r lim is the current limit resistor. r lim is connected from the ilim pin to ground. r o is the output load line resistance. i lim is the current limit set point. this is the peak inductor current that will trip current limit. current monitor the ADP3209D has output current monitor. the imon pin sources a current proportional to the total inductor current. a resistor, r mon , from imon to fbrtn sets the gain of the output current monitor. a 0.1 f is placed in parallel with r mon to filter the inductor current ripple and high frequency load transients. since the imon pin is connected directly to the cpu, it is clamped to prevent it from going above 1.15v. the imon pin current is equal to the r lim times a fixed gain of 10. r mon can be found using the following equation: r mon 1.15 v r lim 10 r o i fs (eq. 29) where: r mon is the current monitor resistor. r mon is connected from imon pin to fbrtn. r lim is the current limit resistor. r o is the output load line resistance. i fs is the output current when the voltage on imon is at full scale. feedback loop compensation design optimized compensation of the ADP3209D allows the best possible response of the regulator?s output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. with the multi ? mode feedback structure of the ADP3209D, it is necessary to set the feedback compensation so that the converter?s output impedance works in parallel with the output decoupling. in addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). a type iii compensator on the voltage feedback is adequate for proper compensation of the output filter. figure 26 shows the type iii amplifier used in the ADP3209D. figure 27 shows the locations of the two poles and two zeros created by this amplifier. figure 26. voltage error amplifier r a adp3209 reference voltage output voltage c a c b c fb r fb comp fb 2 3 voltage error amplifier figure 27. poles and zeros of voltage error amplifier gain 0db frequency f p1 f z2 f p2 f z1 ?20db/dec ?20db/dec the following equations give the locations of the poles and zeros shown in figure 27: f z1 1 2 c a r a (eq. 30) (eq. 31) (eq. 32) (eq. 33) f z2 1 2 c fb r fb f p1 1 2 c a c b r fb f p2 c a c b 2 r a c b c a the expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning procedure for ADP3209D section): r e r o a d r ds r l v rt v id (eq. 34) 2 l (1 ( n d) ) v rt c x r o v vid
ADP3209D http://onsemi.com 23 t a c x (r o r ) l x r o r o r r x (eq. 35) t b (r x r r o ) c x (eq. 36) t c v rt l a d r ds 2 f sw v vid r e (eq. 37) t d c x c z r o 2 c x (r o r ) c z r o (eq. 38) where: r? is the pcb resistance from the bulk capacitors to the ceramics and is approximately 0.4 m (assuming an 8 ? layer motherboard). r ds is the total low ? side mosfet for on resistance. a d is 5. v rt is 1.25 v. l x is the esl of the bulk capacitors (450 ph for the two panasonic sp capacitors). the compensation values can be calculated as follows: c a r o t a r e r b (eq. 39) r a t c c a (eq. 40) c b t b r b (eq. 41) c fb t d r a (eq. 42) the standard values for these components are subject to the tuning procedure described in the tuning procedure for ADP3209D section. c in selection and input current di/dt reduction in continuous inductor ? current mode, the source current of the high ? side mosfet is approximately a square wave with a duty ratio equal to v out /v in . to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the maximum rms capacitor current occurs at the lowest input voltage and is given by: i crms d i o 1 d 1 (eq. 43) i crms 0.15 15 a 1 0.15 1 5.36 a where i o is the output current. in a typical notebook system, the battery rail decoupling is achieved by using mlc capacitors or a mixture of mlc capacitors and bulk capacitors. in this example, the input capacitor bank is formed by four pieces of 10 f, 25 v mlc capacitors, with a ripple current rating of about 1.5 a each. soft transient setting as described in the theory of operation section, during the soft transient, the slew rate of the v ccgfx reference voltage change is controlled by the st pin capacitance. the st pin capacitance is set to satisfy the slew rate for a fast exit as follows: c st 7 a slewrate (eq. 44) where: 7.5 a is the source/sink current of the st pin. slew rate is the voltage slew rate after a change in vid voltage and is defined as 10 mv/ a in the imvp ? 6+ specification. c st is 750 pf, and the closest standard capacitance is 680 pf. tuning procedure for ADP3209D set ? up and test the circuit 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. connect a dc load to the circuit. 3. turn on the ADP3209D and verify that it operates properly. 4. check for jitter with no load and full load conditions. set the dc load line 1. measure the output voltage with no load (v nl ) and verify that this voltage is within the specified tolerance range. 2. measure the output voltage with a full load when the device is cold (v flcold ). allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (v flhot ). if the difference between the two measured voltages is more than a few millivolts, adjust r cs2 using equation 45. r cs2(new) r cs2(old) v nl v flcold v nl v flhot (eq. 45) 3. repeat step 2 until no adjustment of r cs2 is needed. 4. compare the output voltage with no load to that with a full load using 5 a steps. compute the load line slope for each change and then find the average to determine the overall load line slope (r omeas ). 5. if the difference between r omeas and r o is more than 0.05 m , use the following equation to adjust the r ph values: r ph(new) r ph(old) r omeas r o (eq. 46) 6. repeat steps 4 and 5 until no adjustment of r ph is needed. once this is achieved, do not change r ph , r cs1 , r cs2 , or r th for the rest of the procedure.
ADP3209D http://onsemi.com 24 7. measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. set the ac load line 1. remove the dc load from the circuit and connect a dynamic load. 2. connect the scope to the ou tput voltage and set it to dc coupling mode with a time scale of 100 s/div. 3. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 4. measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). try to use a vertical scale of 100 mv/div or finer. 5. the resulting waveform will be similar to that shown in figure 28. use the horizontal cursors to measure v acdrp and v dcdrp , as shown in figure 28. do not measure the undershoot or overshoot that occurs immediately after the step. figure 28. ac load line waveform v dcdrp v acdrp 6. if the difference between v acdrp and v dcdrp is more than a couple of millivolts, use equation 47 to adjust c cs . it may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). c cs(new) c cs(old) v acdrp v dcdrp (eq. 47) 7. repeat steps 5 and 6 until no adjustment of c cs is needed. once this is achieved, do not change c cs for the rest of the procedure. 8. set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning v acdrp and v dcdrp are equal. 9. ensure that the load step slew rate and the power ? up slew rate are set to ~150 a/ s to 250 a/ s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some dynamic loads have an excessive overshoot at power ? up if a minimum current is incorrectly set (this is an issue if a vtt tool is in use). set the initial transient 1. with the dynamic load set at its maximum step size, expand the scope time scale to 2 s/div to 5 s/div. this results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after v droop (see figure 29). figure 29. transient setting waveform, load step v droop v tran1 v tran2 2. if both overshoots are larger than desired, try the following adjustments in the order shown. a. increase the resistance of the ramp resistor (r ramp ) by 25%. b. for v tran1 , increase c b or increase the switching frequency. c. for v tran2 , increase r a by 25% and decrease c a by 25%. if these adjustments do not change the response, it is because the system is limited by the output decoupling. check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. for load release (see figure 30), if v tranrel is larger than the value specified by imvp ? 6+, a greater percentage of output capacitance is needed. either increase the capacitance directly or decrease the inductor values. (if inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures).
ADP3209D http://onsemi.com 25 figure 30. transient setting waveform, load release v droop v tranrel layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations 1. for best results, use a pcb of four or more layers. this should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. 2. when high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. if critical signal lines (including the output voltage sense lines of the ADP3209D) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. an analog ground plane should be used around and under the ADP3209D for referencing the components associated with the controller. this plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. 5. the components around the ADP3209D should be located close to the controller with short traces. the most important traces to keep short and away from other traces are those to the fb and csfb pins. refer to figure 25 for more details on the layout for the csfb node. 6. the output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. avoid crossing signal lines over the switching power path loop, as described in the power circuitry section. power circuitry 1. the switching power path on the pcb should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise ? related operational problems in the power ? converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. the use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. when a power ? dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer heat to the surrounding air. to achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the mosfets on the opposite side of the pcb. in addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. for best emi containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. signal circuitry 1. the output voltage is sensed and regulated between the fb and fbrtn pins, and the traces of these pins should be connected to the signal ground of the load. to avoid differential mode noise pickup in the sensed signal, the loop area
ADP3209D http://onsemi.com 26 should be as small as possible. therefore, the fb and fbrtn traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be kelvin connected to the center point of the copper bar, which is the v ccgfx common node for the inductor. 3. on the back of the ADP3209D package, there is a metal pad that can be used to heat sink the device. therefore, running vias under the ADP3209D is not recommended because the metal pad may cause shorting between vias. ordering information device temperature range package package option shipping ? ADP3209Djcpz ? rl 0 c to 100 c 32 ? lead frame chip scale package [lfcsp_vq] cp ? 32 ? 2 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *the ?z? suffix indicates pb ? free part.
ADP3209D http://onsemi.com 27 package dimensions lfcsp32 5x5, 0.5p case 932ae ? 01 issue a seating note 4 m 0.20 c (a3) a a1 d2 b 1 9 17 32 e2 32x 4x l 32x bottom view indicator top view side view d a b e 0.20 c pin one reference 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 5.00 bsc d2 2.95 3.25 e 5.00 bsc 3.25 e2 2.95 e 0.50 bsc h ??? 12 k 0.20 ??? plane l 0.30 0.50 m ??? 0.60 d1 4.75 bsc e1 4.75 bsc d1 e1 h pin 1 m 4x k note 3 dimensions: millimeters 0.50 3.14 0.28 3.14 32x 0.63 32x 5.30 5.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 pitch package outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ADP3209D/d all brand names and product names appearing in this document are registered trademarks or trademarks of their respective holder s. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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